1. Field of the Invention
This invention relates generally to multi-processor computer systems. More specifically, it relates to multi-processor reduced instruction set computer (RISC) systems which use fixed length instructions to control special purpose Very Large Scale Integration (VLSI) gate arrays.
2. Background Information
Many computer systems today are composed of multiple processing units in order to increase their processing power. These programmable processors often must interact with hardwired logic such as VLSI gate arrays. Some functions of complex computer systems are performed by such hardware because of the increased speed capabilities this hardware provides. However, other functions may be better implemented in software or firmware because of the flexibility software or firmware provides. In a large computer system such as the Extended Processing Complex (XPC), a file cache system designed to operate in conjunction with a 2200 Series computer system, both of which are available from Unisys Corporation, some capabilities of embedded subsystems are implemented in a combination of hardware and software/firmware. These subsystems performed required functions as components of the larger system. These subsystems combine the increased speed of hardware implementations with the flexible nature of programming to efficiently satisfy subsystem requirements.
Fault detection capabilities are also important for such subsystems. These subsystems must detect any errors that occur during processing at the earliest possible time, before the error propagates throughout the entire system, potentially corrupting critical data. Consonant with increased fault detection capabilities is the requirement for the subsystem to communicate with the system maintenance function of the larger computer system wherein the subsystem is embedded to report any faults that are detected. Because commercial microprocessors such as the Intel X86-series or Motorola 68000-series microprocessors do not easily support unique system maintenance functions, a custom microprocessor-based subsystem is required that not only minimizes error latency times but also reports the error in a manner that is easily processed by other functions within the larger system.
In addition, the subsystem disclosed herein must be capable of processing either 32-bit or 36-bit data words. Since Intel X86-series and Motorola 68000-series microprocessors operate on 32-bit words, they would be unsuitable for processing the 36-bit data words supported by the 2200 Series computer systems that the present subsystem must interact with. The microprocessor used in the present invention must be able to be configured for either 32-bit or 36-bit modes of operation by setting an external pin.
Therefore, a custom microprocessor-based system is required to meet speed requirements and it must contain simple logic in order to minimize development costs. A reduced instruction set computer (RISC) satisfies these requirements. RISC processors implement a small set of very basic instructions to minimize instruction decode and execution times. RISC processors operate on fixed length instructions that support only one or two operands. Because of the simplicity of the instruction set, the logic design of a RISC processor is hardwired rather than microprogrammed. Thus, the overall speed of the processor is improved.
The novel arrangement for a multiprocessor data processing system disclosed herein fulfills the above stated requirements and avoids the problems inherent in using existing prior art microprocessors and computer architectures.